1. Field of the Invention
The present invention relates to an ATM segmentation and re-assembly method and apparatus, more particularly to such a method and apparatus in which the components of the apparatus may be simplified.
2. Description of the Related Art
Asynchronous transfer mode (ATM) has become increasingly important over the past few years in the telecommunications industry for the transport of voice and data traffic around telecommunications networks. It is also starting to be used in local area networks to connect personal computers and other equipment together as an alternative to Ethernet. These networks are all aimed at higher and higher bit rates, both measured as the network gross bit rate and the bit rate per user. Furthermore, large numbers of virtual channels are provided on each physical link.
Another application for ATM is the transport of audio/video and other data to and from a digital set top box (STB) or other similar consumer equipment.
For general consumer equipment, cost is very important. Furthermore, for devices such as audio/video set top boxes, it is acceptable to limit the bit rate and number of virtual channels to much smaller numbers than would otherwise be used.
Integrated circuits are available for the combined process of segmentation and re-assembly (SAR) of ATM signals. These SAR integrated circuits determine whether a received ATM cell belongs to a virtual channel being used, extract the ATM payload of a required cell and add the data to the end of previously received data. Furthermore, when a cell is the last cell of a packet, they check the length and correction codes of that packet before passing the entire packet on to the next processing stage.
In order to buffer all the data of a packet as it is reassembled, a significant amount of memory is required. Furthermore, in the segmentation process, more memory is required for the buffers to hold the data packets which are to be transmitted.
It is possible to provide some dedicated memory on a separate integrated circuit, but this adds cost to the system. It is also possible to share the main memory with the processor, but this can effect the processor performance, because the memory bus has to be shared. Both methods also have the disadvantage that the SAR integrated circuit must have sufficient pins to drive the memory bus.
Currently available integrated circuits are thus relatively complicated and expensive, particularly since they are increasingly designed to handle very high bit rates and large numbers of virtual channels.
The present invention is based on a recognition of the above problem and also a recognition of the need for a simplified design, with particular application to the lower bit rates and numbers of virtual channels required for audio/video transmission.
According to the present invention, there is provided a method of reducing the workload of an ATM assembly circuit for assembling ATM packets relating to respective virtual channels from interleaved ATM cells containing ATM payloads, the method comprising:
configuring the circuit to a) check each interleaved ATM cell of an ATM packet of a selected virtual channel with respect to the ATM trailer information contained in the ATM cells of said ATM packet without deinterleaving the ATM cells, b) generate check data for each ATM cell indicating the results of the checking and c) transmit the interleaved ATM cell payloads together with the check data; and
providing a processor to receive the ATM cell payloads and check data and to store the ATM cell payloads in a memory in a deinterleaved state.
By virtue of this, it is also possible to provide a method of assembling ATM packets relating to respective virtual channels from interleaved ATM cells containing respective ATM payloads, the method comprising:
receiving the interleaved ATM cells;
checking each ATM cell of an ATM packet of a selected virtual channel with respect to the ATM packet trailer information contained in the ATM cells of said ATM packet;
generating check data for each ATM cell indicating the results of the step of checking;
outputting the interleaved ATM cell payloads, together with the check data to a main processor; and
operating the main processor to deinterleave the ATM cell payloads of respective virtual channels to assemble ATM packets of respective virtual channels.
Hence, also, there may also be provided an ATM circuit for use in re-assembly of ATM packets from ATM cells containing ATM payloads, the circuit comprising:
an input unit for receiving interleaved ATM cells derived from ATM packets relating to respective virtual channels; and
a checker for checking the ATM cells of an ATM packet of a selected virtual channel with respect to ATM packet trailer information contained in the ATM cells of said ATM packet; wherein
the ATM circuit is configured to output the ATM cell payloads in the original interleaved state.
That circuit may then be provided in a complete ATM re-assembly circuit additionally comprising a main processor for controlling the ATM re-assembly circuit;
a memory for storing deinterleaved ATM cell payloads of ATM packets; wherein
the main processor is configured to receive the ATM payloads output by the ATM circuit and to deinterleave the ATM cell payloads by storing the ATM cell payloads in the memory.
In this way, a much simplified ATM circuit may be used without the need for large buffer memories.
The ATM circuit is responsible for checking the cell headers to determine the cells of required virtual channels and then checks the correction and length codes for the packets, without deinterleaving them. As each ATM cell passes through the ATM circuit, CRC information for the complete packet is built up and the length of the packet is counted. Therefore, when the last cell of a packet passes through the ATM circuit, it is possible for the ATM circuit to establish whether the packet is complete and correct and to indicate this to the further processing. The ATM circuit does not need to deinterleave and store an entire packet before carrying out these functions and, therefore, does not need the use of large buffer memories.
As mentioned above, for audio/video applications, the data rates are relatively low. The present invention can make use of this to particular advantage, since the main processor can easily handle the necessary data rates. In particular, a main processor, which would otherwise be relatively underworked, can be utilized to conduct the deinterleaving of cells.
The cell headers may be output from the ATM circuit merely with additional data indicating the results of the checks made on the ATM packets. However, since by that stage the ATM cell payloads have already been checked for errors, the ATM cell headers may be modified and the modified cell headers be stripped of the cell error correction codes.
In general, the ATM system may allow for large numbers of virtual channels, whereas for certain applications, such as audio/video applications, an ATM circuit may only operate on a few virtual channels. In these situations, it may be advantageous to modify the cell headers to indicate the virtual channels in a more simple way. In particular, since fewer virtual channels may need to be distinguished, shorter codes may be used to indicate those virtual channels.
Preferably, the ATM circuit is provided as a single integrated circuit. Such a circuit is relatively simple to construct for the reasons discussed above and, therefore, will be much cheaper for applications in set top boxes than general purpose ATM circuits.